In civil aircraft operations where system safety is a paramount concern, it important that GPS receivers not be allowed to operate in a defective fashion that outputs potentially hazardous and misleading information (HMI) to a pilot. Thus, the probability of a GPS receiver outputting such information is typically specified (e.g., less than 10−5 per flight hour) by regulations governing civil aviation.
The Federal Aviation Administration (FAA) has developed certification procedures for GPS airborne receivers using the Standard Positioning Service (SPS) for Instrument Flight Rules (IFR) operation in the National Airspace System (NAS), embodied in Technical Standard Orders (TSOs) C129a, C145, and C146. The certification of a GPS airborne receiver depends in part on its built-in test (BIT) capability.
As GPS receivers become more complex, the difficulty in achieving sufficient test coverage increases. For example, military GPS receivers may have Selective Availability/Anti-Spoof Module (SAASM) capability, or M-Code processing capability.
SAASM and M-code technologies require additional components for signal processing and computation that may be employed in either the analog or digital portions of the signal path of a GPS receiver, and must be accounted for in a system providing a complete built. However, the ability to provide built-in testing of these technologies is lacking in the prior art.
Thus a need exists for a system and method for testing a GPS receiver that provides an improved BIT capability. There is also a need for system and method that provides a BIT capability for both the analog and digital portions of the signal path in a GPS receiver.